YY open research · v0.1.0
Analog matrix multiplication. Evidence attached.
A behavioral mixed-signal matrix model, driver contract, reproducible calibration experiments, and open-silicon roadmap for inference and hybrid-training research. The public release is meant to make the assumptions inspectable before anyone treats simulation as silicon.
Stage: Behavioral-model released. This is not a chip announcement, benchmark, or fabrication result.
- Model the nonidealities
- Publish the interface
- Advance only on evidence
Released evidence
One executable baseline, three connected layers
The current release joins the research model to the software and digital boundaries a physical experiment would need. It does not fill the missing analog core with a hidden digital multiplier.
Deterministic 8 × 8 model
Signed fixed-point matrix-vector operations with declared quantization, mismatch, offset, noise, drift, clipping, ADC, and calibration settings.
Driver-facing contract
A twelve-register specification, portable C interface, synthesizable digital control shell, and an explicit black-box boundary where a future analog core would connect.
Reproducible receipts
Synthetic experiments retain configuration, seeds, inputs, weights, ideal and observed outputs, error metrics, and a canonical SHA-256 receipt.
Architecture disclosed
A differential charge-domain concept, still unverified
The proposed ordinary-CMOS path uses signed switched-capacitor branches, row DAC voltages, paired column accumulators, a time-multiplexed differential readout, and per-column affine calibration. The first physical candidate is a deliberately small 4 × 4 characterization macro—not an accelerator product.
The point of publishing this direction now is to expose the assumptions, likely failure modes, and test boundary. Capacitor mismatch, switching error, parasitics, conversion overhead, calibration cost, and data movement may invalidate the approach. A negative result would still be a research result if it is measured and reported honestly.
Inference and training boundary
Hybrid training behavior, not analog training silicon
The runtime models forward W·x and transpose Wᵀ·g operations. A host computes outer-product updates, quantizes them, and reloads digital weight codes. That supports hardware-aware and hardware-in-the-loop research without claiming on-chip gradient computation or analog weight updates.
- No verified transistor-level design or PDK implementation
- No physical layout, fabricated device, or measured silicon
- No measured speed, accuracy, energy, area, effective-bit, or yield result
- No on-chip analog weight update, gradient engine, or complete training accelerator
Public maturity gates
The roadmap gets harder before the claims get larger
Later stages remain blocked until their evidence exists. Open PDK and shuttle programs are watch paths only; eligibility, schedule, pin fit, cost, and fabrication are not yet verified or authorized.
Behavioral model
Released now: executable model, calibration path, interface contract, tests, and synthetic evidence.
SPICE verification
Planned gate: choose supported devices and conversion assumptions, then test the concept against declared corners and Monte Carlo conditions.
Layout verification
Future gate: DRC/LVS-clean layout, extracted simulation, pin fit, and a documented test plan for a 4 × 4 characterization macro.
Fabricate, then measure
Blocked until the earlier gates pass and a tapeout path is authorized. Any performance claim must come from a named workload and public measurement boundary.
Two future go/no-go targets are public: at least six effective bits with at least sixteen active elements under a declared workload, and at least a 3× whole-system useful-MAC energy advantage over a named digital baseline after conversion, memory, control, calibration, and repeats are counted. These are targets, not present results.
Reproduce the baseline
The receipt is part of the result
Python 3.11 and 3.12 CI regenerate the same checked synthetic receipt. Reporting values are normalized only at the canonical serialization boundary; that rule is not a physical-accuracy claim.
- Install
python -m pip install -e .- Run
python -m analog_matmul_lab baseline- Verify
python scripts/check_baseline_receipt.py- Receipt SHA-256
2360b03babc31a438513230b78c736d7d487944a5874ad16ce45a59025b753c0
Open hardware and software
Review it, reproduce it, or contribute to it
Hardware-design material uses CERN-OHL-P-2.0. Software, tests, portable interfaces, data formats, and general documentation use Apache-2.0. The tagged repository is an intentional public technical disclosure; it makes no warranty about legal effect, novelty, patentability, or fitness for use.
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